Characterization of high-frequency interconnections running near chips embedded in printed circuit boards
The ever increasing demand for lighter, more portable, cheaper and faster systems and the coinciding miniaturization of electronic circuits, is the driving force behind the invention of advanced packaging concepts. One of these new technologies is the embedding of chips in one ore more layers of a printed circuit board (PCB). Interconnecting the chips is realized by metalized vias, allowing the connections between the different layers and the components to remain as short as possible. The use of embedded components results in a three-dimensional packaging technology. This not only minimizes the length of the interconnections between the chip and the board, but also the length of the signal path between the different components
An embedded chip in the build-up layers of a PCB
An embedded chip in core layers of a PCB
The goal of this master thesis is the detailed study of the influence of embedded chips on the propagation behavior of high-frequency signals on tracks running over and under the chips.
The European project HERMES aims to industrialize the technology process for chip embedding in printed circuit boards. One of the research activities within the project is the high-frequency characterization of embedded dies. For this purpose, the research group Cmst has developed a series of dedicated test boards with embedded chips and measured these boards over a broad frequency range (100 MHz tot 50 GHz). The measurements correspond well to a closed-form model, however, the accuracy of this model is limited and it does not take into account the metalization on the chip. A more advanced model with higher accuracy would allow for a better agreement with the measurement results.
Cross section of a copper track above an embedded chip
The INTEC research group on Electromagnetics has a broad experience in accurate modelling and characterization of printed circuits. Recently, a powerful software tool for fast and reliable calculation of MIS structures (Metal-Insulator-Semicondcutor) was developed. A critical breakthrough was the introduction of Dirichlet-to-Neumann (DtN) boundary operator, which made it possible to accurately describe both semiconducting and highly conductive materials. The DtN method is internationally recognized as essential for the modeling of high-speed on-chip and on-board interconnections. As such, it will be applied in this master thesis to verify the measurement results.
After a short introductory period, the student will make a thorough analysis of the measurement results to determine the possible presence of irregularities or inaccuracies. If necesary, some of these inaccuracies can be corrected using existing de-embedding techniques. Once the measurement results are approved, a comparison between measurements and simulation based on simple test structures can be started. Since some of the material parameters are not fully known, an optimization method needs to be developed based on the available test structures. As a final step, the measurement results for the test structures with embedded chips are compared to the simulation results of the software tool.
This master thesis is a cooperation between two research groups, presenting the opportunity to explore all aspects of this research topic and to build a broad knowledge on the subject. Certain topics can be highlighted, depending on the interest of the student.
high-frequency, advanced packaging, simulation
Technicum + home.