Study and design of a full manageable telecom power supply unit (PSU) by making use of an FPGA

Study and design of a full manageable telecom power supply unit (PSU)

by making use of an FPGA



1 or 2


Key words:

Mixed analog/digital electronics, filter design, FPGA



Switched mode PSU (SM-PSU) modules are often used in the telecom sector for converting the main voltage (-48 VDC) to several lower voltages for the ICs in the same equipment (e.g. 3.3V, 1.25V, …). Nowadays a lot of focus has been brought to the standardization of those SM-PSU modules. The two well known standardization groups that succeeded in this are the Point-Of-Load Alliance (POLA) and Distributed-power Open Standard Alliance (DOSA).


There is also a tendency that SM-PSU modules become more and more intelligent by the implementation of some management features. The communication between those modules happens over a digital interface. Some effort has been spent to standardize the communication interfaces between those modules. An example of such standardization is the Power Management Bus (PMBus).


Those fully manageable digital SM-PSU modules are already available in large numbers on the market. They are mostly built up by making use of a special purpose micro-controller device (e.g. Microchip). The downside of those digital SM-PSU solutions are that they are more costly compared to the conventional SM-PSU solutions and does not lend itself to standardization. In stead of using those micro-controllers, one could use an FPGA, which is often already available in the hardware. It is very interesting in a cost aspect and tends itself to standardize which is nothing more then the continuation towards the standardization.


The aim of this master thesis is to design, simulate, build and test an FPGA controlled PSU. Challenges are

-        getting a stable feedback circuit (to maintain the output voltage at changing loads).

-        implementing the feedback circuit via the FPGA in a safe way (the FPGA should be galvanically separated from the -48 V input)

-        designing a start-up solution (the FPGA needs a low voltage, but this voltage is not yet available at the startup of the system).


This thesis involves, at first, an investigation of the PSU requirements and a theoretical study of a full converter design. Later on, possible controlling architectures are evaluated through simulation and a prototype of the most promising design is build. Subsequently, this prototype is extensively tested (and modified if necessary). In the final phase, all work is summarized into a master thesis and presented.



at home + CMST (Zwijnaarde) + Alcatel-Lucent (Antwerp)